Analyze the basic structure of FPGA

First, the basic structure of FPGA

The FPGA consists of six parts, which are programmable input/output units, basic programmable logic units, embedded block RAMs, abundant wiring resources, underlying embedded functional units, and built-in dedicated hard cores.

Each unit is described as follows:

1. Programmable input/output unit (I/O unit)

At present, most FPGA I/O units are designed to be programmable mode, that is, through the flexible configuration of software, can adapt to different electrical standards and I/O physical characteristics; can adjust the matching impedance characteristics, pull-up resistor; can adjust the output driver The size of the current.

2. Basic Programmable Logic Unit The basic programmable logic unit of the FPGA consists of a lookup table (LUT) and a register (Register). The lookup table performs pure combinational logic functions. FPGA internal registers can be configured as synchronous/asynchronous reset and set, clock enabled flip-flops, or as latches. FPGAs generally rely on registers to complete synchronous timing logic designs. In general, the configuration of the classic basic programmable unit is a register plus a lookup table, but the internal structure of the register and the lookup table of different manufacturers have certain differences, and the combination mode of the register and the lookup table is also different.

An important aspect of learning the LUT and Register ratios of the underlying configuration cells is the device selection and sizing. In addition to the basic programmable logic unit inside the FPGA, there are embedded RAM, PLL or DLL, dedicated Hard IP Core, these modules can also equivalent to a certain scale of the system gate, so a simple scientific method is to use The number of registers or LUTs measured for the device.

3. Embedded block RAM

Most FPGAs now have embedded block RAM. Embedded block RAM can be configured as single-port RAM, dual-port RAM, pseudo dual-port RAM, CAM, FIFO, and other storage structures.

CAM is content address memory. The data written to the CAM is compared with each of its internally stored data and returns the address of all internal data that is the same as the port data. Simply put, RAM is a write address, a storage unit for reading data; CAM and RAM are just the opposite.

In addition to block RAM, Xilinx and Lattice FPGAs can also flexibly configure LUTs into RAM, ROM, FIFO, and other memory structures.

4. Rich routing resources Routing resources connect all the units in the FPGA. The length and technology of the connection determine the driving ability and transmission speed of signals on the connection lines. Distribution of wiring resources:

1) global dedicated routing resources: to complete the device's internal global clock and global reset / set the wiring;

2) Long-term resources: used to complete the wiring of some high-speed signals between the device Bank and some second global clock signals (do not know what is the "second global clock signal");

3) Short-term resources: used to complete the logical interconnection and wiring between basic logic units;

4) Others: There are various wiring resources, dedicated clocks, and reset control signal lines inside the logic unit.

Since in the design process, the layout and router automatically selects the underlying unit module used for the connection of available routing resources according to the topological structure and constraint conditions of the input logic netlist, the routing resources are often ignored. In fact, there is a direct relationship between the optimization and use of routing resources and the implementation results.

5. Underlying embedded functional units (the book gives a lot of examples, but these Dongdong depends on which company's which model of the chip is embedded with any resource decision)

6. There are differences between the embedded hard core and the “underlying embedded unit”. The hard cores referred to here are those whose generality is relatively weak. Not all FPGA devices contain hard cores.